Analog Devices ADSP-SC58 Series Hardware Reference Manual page 20

ADSP-SC58x LP DMA Channel List....................................................................................................... 15–3
Block Diagram.......................................................................................................................................... 15–3
External Connections ............................................................................................................................ 15–3
Internal Blocks ...................................................................................................................................... 15–4
Architectural Concepts ............................................................................................................................. 15–4
Link Port Protocol................................................................................................................................. 15–4
FIFO Buffers ........................................................................................................................................ 15–7
Handshake for Link Port Enable Process ............................................................................................... 15–9
Clocking ............................................................................................................................................. 15–10
Multi-Processor Connectivity ............................................................................................................. 15–10
LP Operating Modes ................................................................................................................................ 15–12
LP Data Transfer Modes......................................................................................................................... 15–12
Core Data Transfers ............................................................................................................................ 15–12
DMA Data Transfers........................................................................................................................... 15–12
LP Event Control....................................................................................................................................... 15–13
Interrupt Signals .................................................................................................................................... 15–13
Enabling Link Port Interrupts ............................................................................................................ 15–13
Status and Error Signals.......................................................................................................................... 15–14
LP Programming Model ............................................................................................................................ 15–14
Setting Up a DMA Transmit Operation ................................................................................................. 15–14
Setting Up a DMA Receive Operation.................................................................................................... 15–15
Setting Up a Core Transmit Operation................................................................................................... 15–16
Setting Up a Core Receive Operation ..................................................................................................... 15–16
ADSP-SC58x LP Register Descriptions .................................................................................................... 15–17
Control Register .................................................................................................................................... 15–18
Clock Divider Value Register ................................................................................................................. 15–20
Receive Buffer Register .......................................................................................................................... 15–21
Status Register ....................................................................................................................................... 15–22
Transmit Buffer Register ........................................................................................................................ 15–24
Shadow Input Transmit Buffer Register ................................................................................................. 15–25
xx ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference