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PHY Control 0 Register
The
DMC_PHY_CTL0
RESETDAT (R/W)
Reset Data Capture Logic
Figure 10-30: DMC_PHY_CTL0 Register Diagram
Table 10-40: DMC_PHY_CTL0 Register Fields
Bit No.
(Access)
12
RESETDAT
(R/W)
11
RESETDLL
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register controls programmable PHY features.
15
14
13
12
11
0
0
0
0
31
30
29
28
27
0
0
0
0
Bit Name
Reset Data Capture Logic.
The DMC_PHY_CTL0.RESETDAT bit resets the data capture logic only, including P
and N buffers. If Quickboot is used, this bit does not have any effect. The
DMC_PHY_CTL0.RESETDAT bit is reset by the hardware. A read of this bit returns
zero.
Reset DLL.
The DMC_PHY_CTL0.RESETDLL bit resets DLL control logic only, including the
90 degree DQS shifters. If Quickboot is used, this bit does not have any effect. The
DMC_PHY_CTL0.RESETDLL bit is reset by the hardware a read of this bit returns
zero.
10
9
8
7
6
5
4
0
0
0
0
0
0
0
0
26
25
24
23
22
21
20
19
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x DMC Register Descriptions
3
2
1
0
0
0
0
0
RESETDLL (R/W)
Reset DLL
18
17
16
0
0
0
0
10–71
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