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SPI Functional Description
• Burst transfer mode for non-DMA write accesses
SPI Functional Description
This section provides information on the function of the SPI module.
Shift register functionality
The SPI is essentially a shift register that serially transmits and receives data bits to or from other SPI devices.
During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serial-
ly). A serial clock line synchronizes shifting and sampling of the information on the two serial data lines.
Master slave functionality
During a data transfer, one SPI system acts as the link master which controls the data flow. The other system
acts as the slave, which has data shifted into and out of it by the master. Different devices can take turn being
masters, and one master can simultaneously shift data into multiple slaves (broadcast mode). However, only
one slave can drive its output to write data back to the master at any given time. This rule must be enforced in
the broadcast mode. Several slaves can be selected to receive data from the master in this mode. But only one
slave can be enabled to send data back to the master.
Enhanced operating modes
SPI supports enhanced modes of operation like fast mode, DIOM, and Quad-SPI, and optional flow control.
In fast mode, received data is sampled on the transmit edge instead of the standard receive edge, thus enabling
a full-cycle path for the received data. In DIOM, both MOSI and MISO are configured as input or output
pins, and 2 bits are shifted in or out on each receive or transmit edge. In Quad-SPI mode, SPI_D3:0 are con-
figured as input or output pins and 4 bits are shifted in or out on each receive or transmit edge. A slower slave
can use flow control to stall a faster master device.
Single and multi-master use
The SPI can be used in a single master as well as multi-master environment. The SPI_MOSI, SPI_MISO,
and the SPI_CLK signals are all tied together in both configurations. SPI transmission and reception can be
enabled simultaneously or individually, depending on
mode, several slaves can be enabled to receive, but only one slave must be in transmit mode and driving the
SPI_MISO line.
ADSP-SC58x SPI Register List
The Serial Peripheral Interface (SPI) provides a full-duplex, synchronous serial interface, which supports both mas-
ter/slave modes and multi-master environments. The SPI's baud rate and clock phase/polarities are programmable,
and it has integrated DMA channels for both transmit and receive data streams. A set of registers governs SPI opera-
tions. For more information on SPI functionality, see the SPI register descriptions.
16–2
SPI_RXCTL
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
and
settings. In broadcast
SPI_TXCTL
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