Analog Devices ADSP-SC58 Series Hardware Reference Manual page 461

Sharc+ processor
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Priority ID Mask Register 1
The
register masks the respective ID bits in the
DMC_PRIOMSK
for elevating the access priority of either a single ID or a range of IDs.
ID1MSK[31:16] (R/W)
Mask for SCB ID1
Figure 10-18: DMC_PRIOMSK Register Diagram
Table 10-27: DMC_PRIOMSK Register Fields
Bit No.
(Access)
31:0
ID1MSK
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
0
ID1MSK[15:0] (R/W)
Mask for SCB ID1
31
0
Bit Name
Mask for SCB ID1.
DMC_PRIOMSK
14
13
12
11
10
9
8
7
0
0
0
0
0
0
0
0
30
29
28
27
26
25
24
23
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x DMC Register Descriptions
register. This masking provides
6
5
4
3
2
1
0
0
0
0
0
0
0
0
22
21
20
19
18
17
16
0
0
0
0
0
0
0
10–55

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