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Peripherals
Link Ports (LP)
The
Link Port (LP)
allow the processor to connect to other processors or peripheral link ports using a simple com-
munication protocol for high-speed parallel data transfer. This peripheral allows various I/O peripheral interconnec-
tion schemes to I/O peripheral devices, as well as co-processing and multiprocessing schemes.
Figure 1-17: LP System Diagram
Serial Peripheral Interface Ports (SPI)
The
Serial Peripheral Interface (SPI)
with multiple SPI-compatible devices. The baseline SPI peripheral is a synchronous, four-wire interface consisting of
two data pins, one device select pin, and a gated clock pin. The two data pins allow full-duplex operation to other
SPI-compatible devices. Two extra (optional) data pins are provided on specific SPIs to support quad SPI operation.
Enhanced modes of operation such as flow control, fast mode, and dual-I/O mode (DIOM) are also supported. In
addition, a direct memory access (DMA) mode allows for transferring several words with minimal CPU interaction.
PC_07:00 Pins
PC_13:09 Pins
PE_08:01 Pins
PE_15:11 Pins
PF_01:00 Pins
Figure 1-18: SPI System Diagram
Universal Asynchronous Receiver/Transmitter (UART)
The
Universal Asynchronous Receiver/Transmitter (UART)
style industry-standard UARTs. The UART converts data between serial and parallel formats. The serial communi-
cation follows an asynchronous protocol that supports various word lengths, stop bits, bit rates, and parity-genera-
tion options. The UART includes interrupt-handling hardware. Multiple events can generate interrupts.
The UART is logically compliant to EIA-232E, EIA-422, EIA-485 and LIN standards, but usually requires external
transceiver devices to meet electrical requirements. In IrDA (Infrared Data Association) mode, the UART meets the
half-duplex IrDA SIR (9.6/115.2 Kbps rate) protocol. In multi-drop bus mode, the UART meets the full-duplex
MDB/ICP v2.0 protocol.
1–10
PB_14:07 Pins
LP1_D7:0
PB_15 Pin
LP1_ACK
PC_00 Pin
LP1_CLK
PD_09:02 Pins
LP0_D7:0
PD_10 Pin
LP0_ACK
PD_11 Pin
LP0_CLK
Clocked by CDU0_CLKO8
is an industry-standard synchronous serial link that supports communication
SPIx_SELy
SPIx_SS
SPIx_CLK
PD_01 Pin
SPIx_MOSI
SPIx_MISO
SPIx_Dy
SPIx_RDY
Clocked by SCLK1_0
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
LP
LP DMA Data Interrupts to SEC/GIC
LP Status Interrupts to SEC/GIC
LP0/1_DMA Triggers to/from TRU Slaves/Masters
System MMR Write-Protection (WP3-6) from SPU
Enable Secure Peripheral (SECUREP3-6) from SPU
SPI
SPI TX/RX DMA Data Interrupts to SEC/GIC
SPI TX/RX DMA Error Interrupts to SEC/GIC
SPI Status Interrupts to SEC/GIC
SPI Error Interrupts to SEC/GIC
SPIx_TX/RXDMA Triggers to/from TRU Slaves/Masters
System MMR Write-Protection (WP106:101, 99:97) from SPU
Enable Secure Peripheral (SECUREP106:101, 99:97) from SPU
module is a full-duplex peripheral compatible with PC-
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