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Shadow MR Register (DDR2/LPDDR), Shadow MR0 Register (DDR3)
The
register in the DMC shadows the MR register in the SDRAM when the DMC is in DDR2 mode or
DMC_MR
LPDDR mode (DMC_CTL.LPDDR =0 or =1 and DMC_CTL.DDR3EN =0) or DDR3 mode
(DMC_CTL.DDR3EN =0 or =1 and DMC_CTL.LPDDR =0). If unmasked by the corresponding bit in the shadow
mask register (DMC_MSK.MR =1), a write to
terface. If masked, a write to
PD (R/W)
Active Power Down Mode
WRRECOV (R/W)
Write Recovery
DLLRST (R/W)
DLL Reset
Figure 10-12: DMC_MR Register Diagram
Table 10-21: DMC_MR Register Fields
Bit No.
(Access)
12
PD
(R/W)
11:9
WRRECOV
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DMC_MR
DMC_MR
only updates the register in the DMC, not the register in the SDRAM.
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Active Power Down Mode.
The DMC_MR.PD bit selects the active power-down mode. Note that this parameter
applies only for DDR2/DDR3 mode and is reserved for LPDDR mode. For more in-
formation about this mode, see the data sheet for the SDRAM being used in your sys-
tem.
Write Recovery.
The DMC_MR.WRRECOV bit selects the write recovery time in terms of clock cycles
(t
). Note that this parameter applies only for DDR2/DDR3 mode and is reserved
CK
for LPDDR mode. For more information about this mode, see the data sheet for the
SDRAM being used in your system.
triggers a "mode register set" command on the memory in-
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 Fast Exit (normal)
1 Slow Exit (low power)
0 16 clock cycles for DDR3 only
1 2 Clock Cycles for DDR2 and 5 clock cycles for DDR3
2 3 Clock Cycles for DDR2 and 6 clock cycles for DDR3
3 4 Clock Cycles for DDR2 and 7 clock cycles for DDR3
4 5 Clock Cycles for DDR2 and 8 clock cycles for DDR3
ADSP-SC58x DMC Register Descriptions
1
0
0
0
BLEN (R/W)
Burst Length
CL0 (R/W)
CAS Latency 0
CL (R/W)
CAS Latency
17
16
0
0
10–43
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