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Data Memory Control Register (DMEM_CONTROL)
0xFFE0 0004
DCBS (L1 Data Cache
Bank Select)
This bit has no effect except
when the DMC bits are b#11.
Determines whether Address
bit A[14] or A[23] is used to
select the L1 data cache bank.
0 - If Bit 14 of address is 1,
select L1 Data Memory
Data Bank B; if Bit 14 of
address is 0, select L1 Data
Memory Data Bank A
1 - If Bit 23 of address is 1,
select L1 Data Memory
Data Bank B; if Bit 23 of
address is 0, select L1 Data
Memory Data Bank A
See
"Example of Mapping
Cacheable Address Space into
Data Banks" on page
6-41.
Figure 6-3. L1 Data Memory Control Register
ADSP-BF535 Blackfin Processor Hardware Reference
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X
X
X
X
X
X
X
X
15 14 13 12 11 10
9
8
X
X
X
X
X
X
0
0
X
X
X
X
X
X
X
X
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
Memory
Reset = Undefined
ENDM (Enable Data Memory)
0 - Disable L1 Data Memory
1 - Enable L1 Data Memory
ENDCPLB (Enable DCPLB)
0 - Disable DCPLB. Flush all
dirty cache lines before
disabling
1 - Enable DCPLB. CPLBs
are disabled during reset.
The reset service routine
must enable CPLBs after
adding entries for the
exception and NMI
service routines.
DMC[1:0] (L1 Data Memory
Configure)
00 - Both data banks are
SRAM
01 - Reserved
10 - Data Bank A is cache,
Data Bank B is SRAM
11 - Both data banks are
cache
6-13
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