Analog Devices ADSP-SC58 Series Hardware Reference Manual page 73

Trigger Masking .................................................................................................................................. 32–14
Interrupt Masking ............................................................................................................................... 32–14
Modulator Clock ................................................................................................................................. 32–14
Filter Configuration ............................................................................................................................ 32–14
Primary Filter Parameters.................................................................................................................... 32–15
Primary DMA Configuration and Data Interrupts.............................................................................. 32–15
Secondary Filter Parameters ................................................................................................................ 32–16
Overload Detection ............................................................................................................................. 32–16
ADSP-SC58x SINC Register Descriptions ............................................................................................... 32–17
Bias for Group 0 Register ...................................................................................................................... 32–18
Bias for Group 1 Register ...................................................................................................................... 32–19
Clock Control Register .......................................................................................................................... 32–20
Control Register .................................................................................................................................... 32–22
History Status Register .......................................................................................................................... 32–26
Level Control for Group 0 Register ....................................................................................................... 32–28
Level Control for Group 1 Register ....................................................................................................... 32–31
(Amplitude) Limits for Secondary Filter 0 Register ................................................................................ 32–34
(Amplitude) Limits for Secondary Filter 1 Register ................................................................................ 32–35
(Amplitude) Limits for Secondary Filter 2 Register ................................................................................ 32–36
(Amplitude) Limits for Secondary Filter 3 Register ................................................................................ 32–37
Pair 0 Secondary (Filter) History n Register .......................................................................................... 32–38
Pair 1 Secondary (Filter) History n Register .......................................................................................... 32–39
Pair 2 Secondary (Filter) History n Register .......................................................................................... 32–40
Pair 3 Secondary (Filter) History n Register .......................................................................................... 32–41
Primary (Filters) Head for Group 0 Register .......................................................................................... 32–42
Primary (Filters) Head for Group 1 Register .......................................................................................... 32–43
Primary (Filters) Pointer for Group 0 Register ....................................................................................... 32–44
Primary (Filters) Pointer for Group 1 Register ....................................................................................... 32–45
Primary (Filters) Tail for Group 0 Register ............................................................................................ 32–46
Primary (Filters) Tail for Group 1 Register ............................................................................................ 32–47
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference lxxiii