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ADSP-SC58x PADS Register Descriptions
Peripheral PAD Configuration0 Register
The
register provides several configuration options for the pads and multiplexing for peripherals.
PADS_PCFG0
PUMSIHL (R/W)
Pull-Up Enable for MSI DATA[7:4] bits
PUMSIDLC (R/W)
Pull-Up Enable for MSI DATA[3:0] bits
and CMD Pin
TWI0VSEL (R/W)
TWI0 Voltage Select
TWI1VSEL (R/W)
TWI1 Voltage Select
TWI2VSEL (R/W)
TWI2 Voltage Select
EMACAUXIE (R/W)
Input enable control for PTP_AUXIN
pins
Figure 14-37: PADS_PCFG0 Register Diagram
Table 14-40: PADS_PCFG0 Register Fields
Bit No.
(Access)
17
EMACAUXIE
(R/W)
16
PUTMS
(R/W)
15
PUMSIHL
(R/W)
14
PUMSIDLC
(R/W)
14–106
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Input enable control for PTP_AUXIN pins.
Pull-Up Enable for TMS/SWDIO (debug port).
Pull-Up Enable for MSI DATA[7:4] bits.
Pull-Up Enable for MSI DATA[3:0] bits and CMD Pin.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
9
8
7
6
5
4
3
2
0
0
0
0
0
0
1
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 Disable input
1 Enable input
0 Disable pull-up
1 Enable pull-up
0 Disable pull-up
1 Enable pull-up
0 Disable pull-up
1 Enable pull-up
1
0
0
1
EMAC0 (R/W)
PTP Clock Source 0
EMACRESET (R/W)
Reset Enable for RGMII
EMACPHYISEL (R/W)
Select PHY Interface RGMII/RMII
PWMGPSEL (R/W)
PWM Global Precision Select
17
16
0
1
PUTMS (R/W)
Pull-Up Enable for TMS/SWDIO (debug
port)
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