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SPI Interrupt Signals
• To use some of the features offered by SPI memory devices, programs can first configure the SPI memory de-
vice by setting its control word or sending some commands. Since SPI memory-mapped hardware does not
allow any type of SPI write operations, configure the SPI in non-memory-mapped mode prior to enabling
memory-mapped mode.
• The memory-mapped hardware does not interpret the opcode. It does not check the validity of the timing that
is specified in the
SPI_MMRDH
SPI_MMRDH
register to be consistent with the read-type selected.
• When the core requests the data or code fetch, the memory-mapped transfer depends on cache settings. The
cache configuration register in the SPI memory device must be appropriately configured before enabling mem-
ory-mapped mode. Some of the high performance modes like merge, wrap, and transfer size depend on cache
parameters.
• SPI memory-mapped MDMA reads do not support wrapping. For MDMA reads, limit the
DMA_CFG.MSIZE field to 1 byte, 2 bytes or 4 bytes.
• There is not always tool support to change the SPI memory-mapped hardware setting or cache settings on-the-
fly. Changing these settings can optimize the performance of code that accesses SPI memory in memory-map-
ped mode. It is expected that the SPI memory, SPI peripheral, and cache are programmed to one specific set of
control settings for the whole application. Profiling or benchmarking of the actual application can be done to
find the setting that works best.
SPI Interrupt Signals
The SPI controller supports three types of interrupt request signals that correspond to data, status, and error condi-
tions.
Data Interrupts
The SPI peripheral supports two data interrupt channels – receive and transmit. These interrupt signals are multi-
plexed into the DMA request lines. Since the peripheral interfaces with separate read and write interfaces with
DMA, the read and write data interrupts are independent. When the DMA channels are not used, the interrupts are
routed directly to the system event controller. The interrupts occupy the same vector locations as the corresponding
DMA channels.
Each of the data interrupt requests can be individually controlled. Program the SPI_RXCTL.RDR and
SPI_TXCTL.TDR bit fields for receive and transmit, respectively. When receive is enabled, the RX interrupt re-
quest is issued whenever there is data available in the receive datapath for reading. (The event occurs according to
the SPI_RXCTL.RDR bit setting.) When transmit is enabled, the TX interrupt request is issued whenever the
transmit datapath can be written. (The event occurs according to the SPI_TXCTL.TDR setting.) DMA data inter-
rupts are compatible with second-generation DMA to incorporate urgent data requests and transfer finish interrupt
requests apart from the usual data request interrupts. Transmit interrupt requests operate independently from the
word counter-value in the
16–28
register for a particular opcode. Programs must set the fields of the
SPI_TWC
register.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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