Analog Devices ADSP-SC58 Series Hardware Reference Manual page 882

Table 18-26: 16-bit Split Receive Mode with SPLTWRD = 0, SKIPEN = 0 and SWAPEN = 1
Pin Data SPLTEO=1
(16 bits) SUBSPLTODD=0
SWAPEN=1
SKIPEN=0
SKIPEO=X
DMACFG=1
PRIMARY
DMA
CHANNEL
V
0
Y
0
U
0
Y Y Y
1 0 1
V
1
Y
2
U
1
Y Y Y
3 2 3
V
2
Configuring 16-Bit Split Receive Mode with SPLTWRD=1
For 16-bit split receive mode, the EPPI_CTL.PACKEN bit is not valid. The EPPI always packs two 16-bit words
into one 32-bit word. The EPPI_CTL.SPLTWRD bit is only valid when the EPPI_CTL.DLEN bit =16 bits.
Table 18-27: 16-bit Split Receive Mode with SPLTWRD = 1, SKIPEN = 0 and SWAPEN = 0
Pin Data SPLTEO=1
(16 bits) SUBSPLTODD=0
SWAPEN=0
SKIPEN=0
SKIPEO=X
DMACFG=1
Primary
DMA
Channel
V Y
0 0
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DMACFG=0
SECONDARY PRIMARY
DMA DMA
CHANNEL CHANNEL
V U V U
0 0 0 0
Y Y
0 1
V U V U
1 1 1 1
Y Y
2 3
DMACFG=0
Secondary Primary
DMA DMA
Channel Channel
SPLTEO=1
SUBSPLTODD=1
SWAPEN=1
SKIPEN=0
SKIPEO=X
DMACFG=1
PRIMARY SECONDARY
DMA DMA
CHANNEL CHANNEL
Y Y
0 1
V V
0 1
U U
0 1
Y Y
2 3
SPLT_EVEN_ODD=1
SUBSPLTODD=1
SWAPEN=0
SKIPEN=0
SKIPEO=X
DMACFG=1
Primary Secondary
DMA DMA
Channel Channel
EPPI Mode Configuration
DMACFG=0
PRIMARY
DMA
CHANNEL
Y Y
0 1
V V
0 1
Y Y
2 3
U U
0 1
DMACFG=0
Primary
DMA
Channel
18–43