Analog Devices ADSP-SC58 Series Hardware Reference Manual page 642

ADSP-SC58x PINT Register Descriptions
Table 14-25: PORT_POL_SET Register Fields (Continued)
Bit No.
(Access)
6 PX6
(R/W1S)
5 PX5
(R/W1S)
4 PX4
(R/W1S)
3 PX3
(R/W1S)
2 PX2
(R/W1S)
1 PX1
(R/W1S)
0 PX0
(R/W1S)
ADSP-SC58x PINT Register Descriptions
The Pin Interrupt module (PINT) contains the following registers.
14–70
Bit Name
Port x Bit 6 Polarity Invert Set.
The PORT_POL_SET.PX6 bit enables pin polarity inversion.
Port x Bit 5 Polarity Invert Set.
The PORT_POL_SET.PX5 bit enables pin polarity inversion.
Port x Bit 4 Polarity Invert Set.
The PORT_POL_SET.PX4 bit enables pin polarity inversion.
Port x Bit 3 Polarity Invert Set.
The PORT_POL_SET.PX3 bit enables pin polarity inversion.
Port x Bit 2 Polarity Invert Set.
The PORT_POL_SET.PX2 bit enables pin polarity inversion.
Port x Bit 1 Polarity Invert Set.
The PORT_POL_SET.PX1 bit enables pin polarity inversion.
Port x Bit 0 Polarity Invert Set.
The PORT_POL_SET.PX0 bit enables pin polarity inversion.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 No Effect
1 Set Bit. Set to enable GPIO pin polarity invert.
0 No Effect
1 Set Bit. Set to enable GPIO pin polarity invert.
0 No Effect
1 Set Bit. Set to enable GPIO pin polarity invert.
0 No Effect
1 Set Bit. Set to enable GPIO pin polarity invert.
0 No Effect
1 Set Bit. Set to enable GPIO pin polarity invert.
0 No Effect
1 Set Bit. Set to enable GPIO pin polarity invert.
0 No Effect
1 Set Bit. Set to enable GPIO pin polarity invert.