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SMC Programmable Timing Characteristics
• Pre-setup time = 1 cycle
• Read setup time = 3 cycles
• Read access time = 6 cycles
• Read hold time = 2 cycles
• SMC_B0CTL.RDYPOL =1 (memory is ready when SMC_ARDY =1)
The bus cycles proceed as follows:
• At the start of the pre-setup phase, SMC_AMS[n] asserts, and read address SMC_A01 is presented on the ad-
dress bus.
• At the start of the setup period, SMC_AOE is asserted.
• At the start of the read access, SMC_ARE is asserted.
• The CLKOUT signal is SCLK0_0 which is driven out of the pads. The CLKOUT signal falling edge can be
delayed from the internal SCLK0_0 falling edge. See the data sheet for the specification related to this delay.
All output signals out of the pads, for example SMC_ARE and SMC_AOE, are driven with regard to the falling
edge of CLKOUT.
• The SMC starts sampling the SMC_ARDY signal on every rising edge of internal SCLK0_0 two cycles before
the programmed number of read access cycles expires. The read access is extended (SMC_ARE is kept asserted)
until the SMC samples SMC_ARDY high.
• Once the SMC samples the SMC_ARDY signal (asserted by memory device) high in SCLK0_0, the read signal
is pulled off internally in the SCLK0_0 domain. The total delay between the SMC_ARDY signal going high at
the pads and the deassertion of the SMC_ARE signal at the pads can be a maximum of five SCLK0_0 cycles.
• Read data is latched at the falling edge of CLKOUT on the same edge where the SMC deasserts SMC_ARE.
• Hold bus cycles start after the SMC deasserts the SMC_ARE signal.
• At the end of the hold period, the SMC_AMS[n] and SMC_AOE signals deassert and the SMC goes into the
transition state.
Asynchronous Flash Reads
The Asynchronous Flash Read with Pre-Setup and Pre-Access Cycles figure illustrates a single asynchronous flash
mode read bus cycle.
11–12
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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