Analog Devices ADSP-SC58 Series Hardware Reference Manual page 456

ADSP-SC58x DMC Register Descriptions
Table 10-23: DMC_MR2 Register Fields (Continued)
Bit No.
(Access)
2:0 PASR
(R/W)
10–50
Bit Name
Partial Array Self refresh.
The DMC_MR2.PASR bits select the amount of memory to be refreshed during self
refresh. For more information about this operation, see the data sheet for the SDRAM
being used in your system.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 4 banks: full array, 8 banks: full array
1 4 banks: Half Array (BA[1:0]=00&01), 8 banks: Half
Array (BA[2:0] = 000, 001, 010, &011)
2 4 banks: Quarter Array (BA[1:0]=00), 8 banks: Quarter
Array (BA[2:0] = 000&001)
3 4 banks: not defined, 8 banks: 1/8th array (BA[2:0] =
000)
4 4 banks: 3/4 Array (BA[1:0]=01, 10&11), 8 banks: 3/4
Array (BA[2:0] = 010, 011, 100, 101, 110, &111)
5 4 banks: Half Array (BA[1:0]=10&11), 8 banks: Half
Array (BA[2:0] = 100, 101, 110, &111)
6 4 banks: Quarter Array (BA[1:0]=11), 8 banks: Quarter
Array (BA[2:0] =110 & 111)
7 4 banks: not defined, 8 banks: 1/8th array (BA[2:0] =
111)