Analog Devices ADSP-SC58 Series Hardware Reference Manual page 300

Table 7-27: SEC_SCTL[n] Register Fields (Continued)
Bit No.
(Access)
19:16 GRP
(R/W)
15:8 PRIO
(R/W)
4 ERREN
(R/W)
3 ES
(R/W)
2 SEN
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Group Select.
The SEC_SCTL[n].GRP bits each select a specific group for the interrupt. Each
system interrupt can be assigned to any combination of groups supported by the
SEC_SCTL[n].GRP field.
For example, consider the situation where SEC_SCTL[n].GRP0 represents inter-
rupt group 0, SEC_SCTL[n].GRP1 represents interrupt group 1, and so on. One
group might be used for all enabled interrupts (for example, group 0) and an addition-
al group might be used for all wakeup interrupts (for example, group 1). This ap-
proach supports a model of all interrupts and just the wakeup subset.
Before going to idle or sleep, all non-wakeup interrupts can be masked off to allow on-
ly wakeup interrupts to be enabled for service. Selecting no group (all
SEC_SCTL[n].GRP bits = 0) places the interrupt source in the category of "un-
grouped".
Priority Level Select.
The SEC_SCTL[n].PRIO bits sets the relative priority for an interrupt request. A
pending interrupt request forwards its SEC_SCTL[n].PRIO value to the SEC core
interface.
Error Enable.
The SEC_SCTL[n].ERREN bit permits the SEC_SSTAT[n].ERR status bit to
be set on error detection. If SEC_SCTL[n].ERREN is cleared, no errors are detect-
ed.
Edge Select.
The SEC_SCTL[n].ES bit selects the operational and sensitivity mode of the SEC
source interface input.
Source (signal) Enable.
The SEC_SCTL[n].SEN bit controls whether the system event source input signal
may affect the pending status of the source. Clearing the SEC_SCTL[n].SEN bit
disables the source input signal from affecting the pending status. Setting
SEC_SCTL[n].SEN enables the source input signal to affect the pending status.
ADSP-SC58x SEC Register Descriptions
Description/Enumeration
0 Disable
1 Enable
0 Level Sensitive
1 Edge Sensitive
0 Disable
1 Enable
7–55