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ADSP-SC58x DMC Register Descriptions
Table 10-20: DMC_EMR2 Register Fields (Continued)
Bit No.
(Access)
4:3
TCSR
(R/W)
2:0
PASR
(R/W)
10–42
Bit Name
Temperature Compensated Self-Refresh.
The DMC_EMR2.TCSR bits select the temperature for applying temperature compen-
sated self-refresh when the DMC is in LPDDR mode. (These bits are reserved when
the DMC is in DDR2 mode.) For more information about this operation, see the data
sheet for the SDRAM being used in your system.
Partial Array Self-Refresh.
The DMC_EMR2.PASR bits select the amount of memory to be refreshed during self-
refresh. For more information about this operation, see the data sheet for the SDRAM
being used in your system.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description/Enumeration
0 70 degree C (in LPDDR Mode)
1 45 degree C
2 15 degree C
3 85 degree C
0 Full Array for DDR2 , DDR3, and LPDDR Modes.
Applies to both 4 and 8 bank devices.
1 1/2 Array for DDR2 , DDR3, and LPDDR Modes. For
4 bank devices, BA[1:0] =00 and 01. For 8 bank devi-
ces, BA[2:0] = 000, 001, 010, 011
2 1/4 Array for DDR2 , DDR3, and LPDDR Modes. For
4 bank devices, BA[1:0] = 00. For 8 bank devices,
BA[2:0] = 000 and 001.
3 1/8 Array for 8 DDR2 or DDR3 Banks Only. Reserved
for LPDDR. For 4 bank devices, not defined. For 8
bank devices, BA[2:0] = 000.
4 3/4 Array for DDR2 or DDR3. Reserved for LPDDR.
For 4 bank devices, BA[1:0]=01, 10 and 11. For 8 bank
devices, BA[2:0] = 010, 011, 100, 101, 110, and 111.
5 1/2 Array for DDR2 or DDR3. 1/8 Array for LPDDR.
For 4 bank devices, BA[1:0]=10 and 11. For 8 bank de-
vices, BA[2:0] = 100, 101, 110, and 111.
6 1/4 Array for DDR2 or DDR3. 1/16 Array for
LPDDR. For 4 bank devices, BA[1:0]=11. For 8 bank
devices, BA[2:0] =110 and 111.
7 1/8 array (for DDR2 or DDR3 Banks only); Reserved
(LPDDR)
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