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Table 8-3: ADSP-SC58x Trigger List Masters (Continued)
Trigger ID
Name
61
IIR0_DMA
62
EPPI0_CH0_DMA
63
EPPI0_CH1_DMA
64
LP0_DMA
65
LP1_DMA
66
UART0_TXDMA
67
UART0_RXDMA
68
UART1_TXDMA
69
UART1_RXDMA
70
UART2_TXDMA
71
UART2_RXDMA
72
USB0_DATA
73
USB1_DATA
74
MDMA0_SRC
75
MDMA0_DST
76
MDMA1_SRC
77
MDMA1_DST
78
MDMA2_SRC
79
MDMA2_DST
80
MDMA3_SRC
81
MDMA3_DST
82
EMDMA0_DONE
83
EMDMA1_DONE
84
CTI3_MST0
85
CTI3_MST1
86
CTI3_MST2
87
CTI3_MST3
88
CTI3_MST4
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description
IIR0 DMA
EPPI0 Channel 0 DMA
EPPI0 Channel 1 DMA
LP0 DMA Channel
LP1 DMA Channel
UART0 Transmit DMA
UART0 Receive DMA
UART1 Transmit DMA
UART1 Receive DMA
UART2 Transmit DMA
UART2 Receive DMA
USB0 DMA Status/Transfer Complete
USB1 DMA Status/Transfer Complete
Standard BW MDMA Channel 0 Source (CRC
IN)
Standard BW MDMA Channel 0 Destination
(CRC OUT)
Standard BW MDMA Channel 1 Source (CRC
IN)
Standard BW MDMA Channel 1 Destination
(CRC OUT)
Enh BW MDMA Channel 2 Source
Enh BW MDMA Channel 2 Destination
Max BW MDMA Channel 3 Source
Max BW MDMA Channel 3 Destination
EMDMA0 DMA Done
EMDMA1 DMA Done
CTI3 SYSCTI (CTI3) System Halt Slave 0
CTI3 SYSCTI (CTI3) System Halt Slave 1
CTI3 SYSCTI (CTI3) System Halt Slave 2
CTI3 SYSCTI (CTI3) System Halt Slave 3
CTI3 SYSCTI (CTI3) System Halt Slave 4
TRU Functional Description
Sensitivity
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Level
Level
Edge
Edge
Edge
Edge
Edge
Edge
Edge
8–5
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