Analog Devices ADSP-SC58 Series Hardware Reference Manual page 376

L2 System Memory Architectural Concepts
burst access to an ECC-enabled bank creates an extra latency of two SYSCLK_0 cycles. No extra latency is seen if
the ECC is disabled.
NOTE: Continuous 8/16-bit core access to an ECC-enabled L2 bank is not recommended from a throughput per-
spective.
L2 Memory Controller Block Diagram (Instance)
As shown in the following figure, the L2 controller has two ports that interface to system crossbars. Port 0 is a 64-bit
interface that is dedicated to core traffic, and port 1 is a 32-bit interface that connects through DMA access. For L2
SRAM both ports (0/1) have a read channel and a write channel, for L2 ROM both ports (0/1) have read channels
only. The SRAM/ROM are organized in multiple banks, and each bank has 32K Bytes of data. For ADSP-SC58x
parts, the L2CTL0 has an additional bank for the boot ROM; for ADSP-2158x parts, the L2CTL1 has an addition-
al bank for the boot ROM.
Within each bank, data is organized into 4096 words, with each word comprising 64 bits of data and 14 bits of
ECC checksum. ROM memory is not protected by the ECC scheme. When the L2 controller accesses RAM and
ROM cells, it always reads and writes whole 64-bit words. Despite this, the L2 controller supports 8-, 16-, and 32-
bit reads and writes from cores and system by applying respective data masks.
SCRUB AND
INITIALIZE
LOGIC
SRAM
(128 KB)
Figure 9-2: L2 System Memory Block Diagram
Arbitration and Priority
Each bank of L2 RAM or ROM has an arbiter which receives requests from the two crossbar ports.
Each arbiter follows a fixed priority scheme for giving grants when more than one channel requests the same bank.
The arbiter also supports priority elevation through urgent priority requests.
NOTE: Attempting a write access to both L2 ROM spaces returns an error.
9–4
L2CLK DOMAIN
PORT 1 SCB SLAVE
INTERFACE
(DMA)
CROSS BAR
SRAM SRAM SRAM SRAM
(128 KB) (128 KB) (128 KB) (128 KB)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
L2CLK DOMAIN
PORT 0 SCB SLAVE
INTERFACE
(CORE)
SYSCLK DOMAIN
SRAM SRAM SRAM
(128 KB) (128 KB) (128 KB)
L2CLK DOMAIN
SMRRs
ROM
(512 KB)
SYSCLK
DOMAIN