Analog Devices ADSP-SC58 Series Hardware Reference Manual page 504

Table 11-4: SMC_B0ETIM Register Fields (Continued)
Bit No.
(Access)
10:8 TT
(R/W)
5:4 PREAT
(R/W)
1:0 PREST
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Transition Time.
The SMC_B0ETIM.TT bits select a bus idle time (in SCLK0_0 cycles) that the SMC
extends the SMC_B0ETIM.IT to allow for the subsequent access either using a dif-
ferent transfer direction or accessing a different bank. The transition time is from 1 to
7 SCLK0_0 cycles.
Pre Access Time.
The SMC_B0ETIM.PREAT bits select the pre-access time (in SCLK0_0 cycles) that
the SMC waits after de-asserting the SMC_AOE/ADV pin before asserting the
SMC_ARE/SMC_AWE pin for the current access. The pre-access time is from 0 to 3
SCLK0_0 cycles.
Pre Setup Time.
The SMC_B0ETIM.PREST bits select the pre-setup time (in SCLK0_0 cycles) that
the SMC asserts the SMC_AMS[n] pin before asserting the SMC_AOE/ADV pin for
an access. The pre-setup time is from 0 to 3 SCLK0_0 cycles.
ADSP-SC58x SMC Register Descriptions
Description/Enumeration
0 No bank transition
1 1 SCLK0_0 clock cycle
7 7 SCLK0_0 clock cycles
0 0 SCLK0_0 clock cycles
3 3 SCLK0_0 clock cycles
0 0 SCLK0_0 clock cycles
3 3 SCLK0_0 clock cycles
11–23