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Shared Peripheral Interrupt Enable Clear Register
The
GICDST_SPI_EN_CLR[n]
VALUE[31:16] (R/W)
Shared Peripheral Interrupt Enable
Clear Enable
Figure 7-67: GICDST_SPI_EN_CLR[n] Register Diagram
Table 7-70: GICDST_SPI_EN_CLR[n] Register Fields
Bit No.
(Access)
31:0
VALUE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register provides a clear-enable bit for each interrupt supported by the GIC.
15
X
VALUE[15:0] (R/W)
Shared Peripheral Interrupt Enable
Clear Enable
31
X
Bit Name
Shared Peripheral Interrupt Enable Clear Enable.
Writing 1 to a GICDST_SPI_EN_CLR[n].VALUE bit disables forwarding of the
corresponding interrupt to the CPU interfaces. Reading a bit identifies whether the in-
terrupt is enabled.
14
13
12
11
10
9
8
7
X
X
X
X
X
X
X
X
30
29
28
27
26
25
24
23
X
X
X
X
X
X
X
X
Description/Enumeration
ADSP-SC58x GICDST Register Descriptions
6
5
4
3
2
1
0
X
X
X
X
X
X
X
22
21
20
19
18
17
16
X
X
X
X
X
X
X
7–101
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