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1. Write to the
SPI_SLVSEL
that the desired slaves are properly deselected while the master is configured.
2. The SPI_RXCTL.RTI and SPI_TXCTL.TTI bits determine the SPI initiating mode. The initiating mode
defines the primary transfer channel, and also the initiating condition for the transfer.
3. Write to the SPI_CLK, SPI_CTL, SPI_RXCTL, and
vice as a master and configures the SPI system. It specifies the transfer modes and channels, appropriate word
length, transfer format, baud rate, and other control information.
ADDITIONAL INFORMATION: If SPI_RXCTL.RTI is enabled and SPI_TXCTL.TTI is not, write to
the
SPI_RXCTL
transmit underrun for the first transfer.
4. If SPI_CTL.ASSEL=0, activate the desired slaves by clearing one or more of the
Otherwise, the SPI hardware performs slave activation.
5. The SPI controller then generates the programmed clock pulses on SPI_CLK and simultaneously shifts data
out of SPI_MOSI while shifting data in from SPI_MISO. Before a shift, the shift register is loaded with the
contents of the
SPI_TFIFO
into SPI_RFIFO.
6. Whenever the initiating conditions are satisfied, the SPI continues to send and receive words. If the transmit
buffer remains empty or the receive buffer remains full, the device operates according to the states of the
SPI_TXCTL.TDU and SPI_RXCTL.RDO bits.
7. It is possible to program a secondary channel in addition to the initiating channel. This feature allows usage of
available channel resources for receives or transmits simultaneously with the initiating channel.
Slave Operation in Non-DMA Modes
When a device is enabled as a slave in a non-DMA mode, a transition of the SPI_SS select signal to the active state
(low) triggers the the start of a transfer. Or, the first active edge of SPI_CLK triggers the start, depending on the
state of SPI_CTL.CPHA bit. The interface operates in the following manner.
1. The core writes to the SPI_CTL, SPI_RXCTL, and
of the serial link to be the same as the mode setup in the SPI master.
2. To prepare for the data transfer, the core writes data to be transmitted into SPI_TFIFO.
3. Once the SPI_SS falling edge is detected, the slave starts sending data on active SPI_CLK edges and sam-
pling data on inactive SPI_CLK edges.
4. Reception or transmission continues until SPI_SS is released or until the slave has received the proper num-
ber of clock cycles.
5. The slave device continues to receive or transmit with each new falling edge transition on SPI_SS or active
SPI_CLK edge. If the transmit buffer remains empty or the receive buffer remains full, the device operates
according to the states of the SPI_TXCTL.TDU and SPI_RXCTL.RDO bits.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register, setting one or more of the SPI select enable bits. This operation ensures
register after writing into SPI_CTL, SPI_TXCTL, and
register. At the end of the transfer, the contents of the shift register are loaded
registers. This operation enables the de-
SPI_TXCTL
SPI_TFIFO
registers. The operation defines the mode
SPI_TXCTL
SPI Programming Concepts
registers to prevent a
SPI_SLVSEL
flag bits.
16–31
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