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Memory Mapped Read Header (Only on SPI2)
The
register enables the use of memory-mapped mode. This mode allows direct memory-mapped
SPI_MMRDH
read accesses of an SPI memory device and is primarily used to directly execute instructions from an SPI FLASH
memory without using a low-level software driver. All overhead tasks such as transmission of the read header, pin
turnaround timing and receive data sizing are handled in hardware.
The memory-mapped access mode is enabled by setting the SPI_CTL.MMSE bit. The features within the
SPI_MMRDH
register include a command skip mode, variable length byte addressing, and independent multi-pin
support for command transmission, address transmission and data reception. In addition, the command opcode and
mode bytes are fully programmable.
DMYSIZE (R/W)
Bytes of Dummy/Mode
ADRPINS (R/W)
Pins Used for Address
CMDPINS (R/W)
Pins Used for Command
CMDSKIP (R/W)
Command Skip Enable
WRAP (R/W)
SPI Memory Wrap Indicator
Figure 16-28: SPI_MMRDH Register Diagram
Table 16-26: SPI_MMRDH Register Fields
Bit No.
(Access)
29
CMDPINS
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
12
11
10
0
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
0
Bit Name
Pins Used for Command.
The SPI_MMRDH.CMDPINS bit specifies the number of pins to be used for com-
mand transmission. This bit must be set consistent with the expectations established
by the read opcode. Hardware does not interpret SPI_MMRDH.OPCODE, but rather
relies on this bit to specify behavior. When cleared, it overrides the SPI_CTL.MIOM
bits. When set, it uses bits specified by the SPI_CTL.MIOM bit setting.
9
8
7
6
5
4
3
2
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 Use only one pin: MOSI (overrides SPI_CTL.MIOM
bits)
1 Use pins specified by SPI_CTL.MIOM bits
ADSP-SC58x SPI Register Descriptions
1
0
0
0
OPCODE (R/W)
Read Opcode
ADRSIZE (R/W)
Bytes of Read Address
17
16
0
0
MODE (R/W)
Mode Field
TRIDMY (R/W)
Tristate Dummy Timing
MERGE (R/W)
Merge Enable
16–57
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