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Output Disable and Cross-Over Modes.................................................................................................. 19–26
Brushless DC Motor (Electronically Commutated Motor) Control..................................................... 19–27
Heightened-Precision Edge Placement ................................................................................................... 19–28
Sample Waveforms for High- and Low-Side with Precision Placement................................................ 19–30
Emulation Mode..................................................................................................................................... 19–32
Event Control ........................................................................................................................................... 19–32
Trip Control Unit .................................................................................................................................. 19–33
Programming Model ................................................................................................................................. 19–34
Programming Model for Three-Phase AC Motor Control ...................................................................... 19–34
PWM Initialization for Motor Control ............................................................................................... 19–36
PWM Enable for Motor Control......................................................................................................... 19–38
PWM Response to Sync Interrupt for Motor Control......................................................................... 19–38
PWM Disable (and Stop the Motor) for Motor Control ..................................................................... 19–39
ADSP-SC58x PWM Register Descriptions ............................................................................................... 19–39
Channel A Control Register .................................................................................................................. 19–43
Channel A-High Duty-0 Register .......................................................................................................... 19–45
Channel A-High Heightened-Precision Duty-0 Register ....................................................................... 19–46
Channel A-High Duty-1 Register .......................................................................................................... 19–47
Channel A-High Heightened-Precision Duty-1 Register ....................................................................... 19–48
Channel A-High Full Duty0 Register .................................................................................................... 19–49
Channel A-High Full Duty1 Register .................................................................................................... 19–50
Channel A-Low Duty-0 Register ........................................................................................................... 19–51
Channel A-Low Heightened-Precision Duty-0 Register ......................................................................... 19–52
Channel A-Low Duty-1 Register ........................................................................................................... 19–53
Channel A-Low Heightened-Precision Duty-1 Register ......................................................................... 19–54
Channel A-Low Full Duty0 Register ...................................................................................................... 19–55
Channel A-Low Full Duty1 Register ...................................................................................................... 19–56
Channel B Control Register .................................................................................................................. 19–57
Channel B-High Duty-0 Register .......................................................................................................... 19–59
Channel B-High Heightened-Precision Duty-0 Register ....................................................................... 19–60
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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