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ADSP-SC58x EMAC Interrupt List ...................................................................................................... 31–10
ADSP-SC58x EMAC Trigger List .......................................................................................................... 31–11
EMAC Definitions ................................................................................................................................. 31–11
EMAC Block Diagram and Interfaces..................................................................................................... 31–12
EMAC CORE Subblocks .................................................................................................................... 31–14
EMAC PHY Interface ......................................................................................................................... 31–16
RGMII Board Design Recommendations............................................................................................ 31–17
Clock Sources ...................................................................................................................................... 31–19
EMAC Architectural Concepts ............................................................................................................... 31–20
EMAC Feature Summary .................................................................................................................... 31–20
EMAC System Crossbar Interface (EMAC SCB)................................................................................. 31–20
Priority of SCB Requests ................................................................................................................. 31–21
SCB Interface Programming Options ............................................................................................. 31–22
DMA Bursts Using the SCB Interface ............................................................................................. 31–23
SCB Bus Transaction Status ............................................................................................................. 31–24
Fatal Bus Error ................................................................................................................................. 31–24
DMA Controller (EMAC DMA)......................................................................................................... 31–24
DMA Related Registers.................................................................................................................... 31–25
DMA Descriptors ............................................................................................................................ 31–27
OWN Bit (Ownership) Semaphore ................................................................................................. 31–43
Application Data Buffer Alignment.................................................................................................. 31–44
Buffer Size Calculations .................................................................................................................. 31–44
EMAC FIFO Layer (EMAC MFL) ...................................................................................................... 31–44
FIFO Layer Transmit Path ............................................................................................................... 31–45
FIFO Layer Receive Path.................................................................................................................. 31–46
EMAC CORE .................................................................................................................................... 31–47
EMAC CORE Transmission Engine ................................................................................................ 31–49
Source Address, VLAN, and CRC Insertion, Replacement, or Deletion ........................................... 31–53
EMAC CORE Reception Engine ..................................................................................................... 31–55
EMAC Station Management Interface (SMI) ...................................................................................... 31–65
MDC Clock Frequency .................................................................................................................... 31–66
SMI Write Operation....................................................................................................................... 31–67
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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