Table of Contents
Advertisement
ADSP-SC58x SEC Register Descriptions
SCI Status Register n
The SCI status register (SEC_CSTAT[n]) contains status bits, indicating the operational status of the SCI.
WFI (R/W1C)
Wait For Idle
SIDV (R)
SID Valid
ACTV (R)
ACT Valid
NMI (R/W1C)
Non-Maskable Interrupt
Figure 7-13: SEC_CSTAT[n] Register Diagram
Table 7-12: SEC_CSTAT[n] Register Fields
Bit No.
(Access)
16
NMI
(R/W1C)
12
WFI
(R/W1C)
10
SIDV
(R/NW)
7–34
15
14
13
12
11
0
0
0
0
0
31
30
29
28
27
0
0
0
0
0
Bit Name
Non-Maskable Interrupt.
The SEC_CSTAT[n].NMI bit indicates whether an NMI has occurred since the bit
was last cleared.
Wait For Idle.
The SEC_CSTAT[n].WFI bit indicates (if set) that the SCI is temporarily disabled,
pending a core idle indication. This bit is set when SEC_CCTL[n].WFI is set.
SID Valid.
The SEC_CSTAT[n].SIDV bit indicates (if set) that the current value in the
SEC_CSID[n]
the updating the
SEC_CSTAT[n].SIDV bit is cleared when the
This status indication may be used to extract all pending interrupts in a single inter-
rupt service routine.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
10
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
26
25
24
23
22
21
20
19
0
0
0
0
0
0
0
0
Description/Enumeration
0 No NMI Occurred
1 NMI Occurred
0 Not Waiting
1 Waiting
register is valid. The SCI sets the SEC_CSTAT[n].SIDV bit when
SEC_CSID[n]
register with a new value. The
0 Invalid
1 Valid
2
1
0
0
0
0
ERR (R/W1C)
Error
ERRC (R)
Error Cause
PNDV (R)
PND Valid
18
17
16
0
0
0
SEC_CSID[n]
register is written.
Advertisement
Table of Contents
