Analog Devices ADSP-SC58 Series Hardware Reference Manual page 490

6. At the start of the read access period, the read enable signal, SMC_ARE is asserted.
7. At the end of the read access period, the SMC_ARE signal is deasserted and the read hold period starts. Read
data is latched along with SMC_ARE deasserting.
8. At the end of the read hold period, the SMC pulls the SMC_AMS[n] signal high and appends turnaround
transition cycles unless there is a pending read request to the same bank.
Asynchronous SRAM Reads with IDLE Transition Cycles Inserted
The Asynchronous SRAM Read with IDLE Transition figure shows two consecutive asynchronous SRAM modes
reads to the same bank separated by programmed IDLE transition time cycles.
Figure 11-3: Asynchronous SRAM Read with IDLE Transition
Programmed cycle times are:
• SMC_B0TIM.RST = 2 cycles
• SMC_B0TIM.RAT = 4 cycles
• SMC_B0TIM.RHT = 1 cycle
• IDLE transition time = 2 cycles
At the start of the IDLE transition cycle, the SMC deasserts the SMC_AMS[n] and SMC_AOE signals. The setup
period of the second read starts at the end of the IDLE transition cycle with the assertion of the SMC_AMS[n] and
SMC_AOE signals and a new address on the address bus.
High-Speed Asynchronous SRAM Read Burst
The Fast Asynchronous SRAM Reads, Burst of Four Word figure shows a high-speed asynchronous SRAM read bus
cycle. This read bus cycle is typical for SRAM devices with small access times connecting through SCB read bursts,
especially for boot purposes.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Read Data
Latched
Here
Setup Read Access
2 Cycles 4 Cycles
CLKOUT
A0
SMC_An
SMC_AMSn
SMC_AOE
SMC_ARE
SMC_D15-0 D0
Read Data
Latched
Hold Hold
Here
1 Cycle 1 Cycle
Trams Trams
IDLE Setup Read Access
2 Cycles 2 Cycles 4 Cycles 2 Cycles
A0 + 1
D1
SMC Programmable Timing Characteristics
IDLE
11–9