Analog Devices ADSP-SC58 Series Hardware Reference Manual page 541

Sharc+ processor
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ID Comparison
ID comparison automatically occurs during region-based memory protection. ID matches allow the transaction to
bypass the configured memory protection for that region. The following sections describe the calculation of a write
ID match and read ID match.
Write Transaction
The state of the following values determines the ID value that is compared with the ID of an incoming write trans-
action:
• The SMPU_RCTL[n].WIDCINV bit
• The SMPU_RIDA[n].ID and SMPU_RIDB[n].ID bit fields
• The SMPU_RIDMSKA[n].MSK and SMPU_RIDMSKB[n].MSK bit fields
Write IDA match = ((ID of incoming write transaction AND SMPU_RIDMSKA[n].MSK) ==
(SMPU_RIDA[n].ID AND SMPU_RIDMSKA[n].MSK))
Write IDB match = ((ID of incoming write transaction AND SMPU_RIDMSKB[n].MSK) ==
(SMPU_RIDB[n].ID AND SMPU_RIDMSKB[n].MSK))
Write ID match = (Write IDA match OR Write IDB match) XOR SMPU_RCTL[n].WIDCINV bit
Read Transaction
The state of the following values determines the ID value that is compared with the ID of an incoming read transac-
tion:
• The SMPU_RCTL[n].RIDCINV bit
• The SMPU_RIDA[n].ID and SMPU_RIDB[n].ID bit fields
• The SMPU_RIDMSKA[n].MSK and SMPU_RIDMSKB[n].MSK bit fields
Read IDA match = ((ID of incoming read transaction AND SMPU_RIDMSKA[n].MSK) ==
(SMPU_RIDA[n].ID AND SMPU_RIDMSKA[n].MSK))
Read IDB match = ((ID of incoming read transaction AND SMPU_RIDMSKB[n].MSK) ==
(SMPU_RIDB[n].ID AND SMPU_RIDMSKB[n].MSK))
Read ID match = (Read IDA match OR Read IDB match) XOR SMPU_RCTL[n].RIDCINV
In the two cases described above, the incoming transaction (either write or read) ID is AND'ed with the configured
mask value in protection unit A. It is then compared to the value of the configured ID value which is also AND'ed
with the configured mask value in protection unit A. The mask provides a method to allow a group of IDs to match.
This process is also performed for protection unit B. The two outcomes (from A and B) are then OR'ed together.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SMPU Functional Description
13–5

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