Link Buffer Control Register (Lctl) - Analog Devices ADSP-2106x SHARC User Manual

9 Link Ports
9.2.1

Link Buffer Control Register (LCTL)

The LCTL register contains control bits unique to each link buffer.
Table 9.2 describes the control bits in LCTL.
Bit(s) Name
0-3 *
4-7 *
8-11 *
12-15 *
16-19 *
20-23 *
24 LEXT0
25 LEXT1
26 LEXT2
27 LEXT3
28 LEXT4
29 LEXT5
30-31 reserved
Table 9.2 Link Control Register (LCTL)
* Each four-bit group includes the following control bits for each link buffer
(x=0,1,2,3,4,5):
Bit# Name
0+4x LxEN
1+4x LxDEN
2+4x LxCHEN
3+4x LxTRAN
LCTL Control Bits:
LxEN
Enables a link buffer. As a buffer is disabled (LxEN transitions from
high to low), the LxSTAT and LRERR bits are cleared. When its buffer
is disabled, an assigned link port stops receiving (driving LxACK) or
transmitting (driving LxCLK). To pull the LxACK and LXCLK signals
low, enable the pull down resistors with the LCOM register.
LxDEN Enables the associated DMA channel.
Enables DMA chaining for that channel.
LxCHEN
LxTRAN Selects the direction of the link buffer, link port and DMA
channel: 0 to receive link data, 1 to transmit link data.
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Definition
Link buffer 0 controls
Link buffer 1 controls
Link buffer 2 controls
Link buffer 3 controls
Link buffer 4 controls
Link buffer 5 controls
Extended word size: 1=48-bit transfers, 0=32-bit transfers
Extended word size: 1=48-bit transfers, 0=32-bit transfers
Extended word size: 1=48-bit transfers, 0=32-bit transfers
Extended word size: 1=48-bit transfers, 0=32-bit transfers
Extended word size: 1=48-bit transfers, 0=32-bit transfers
Extended word size: 1=48-bit transfers, 0=32-bit transfers
Definition
LBUFx enable
LBUFx DMA enable
LBUFx chaining enable
LBUFx direction: 1=transmit, 0=receive