Analog Devices ADSP-SC58 Series Hardware Reference Manual page 421

Table 10-9: DDR2, DDR3, and LPDDR Programming (Continued)
PHY/Control- Description
ler
PHY ODT and drive impe-
dance calibration
Controller Enabling DDR3/
DDR2/LPDDR
modes
Controller Configuring
DMC_CTL.RDTOWR
bit field
Controller Configuring
DMC_CFG
fields
Controller Configuring controller
timing parameter reg-
isters
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Registers and Bit
Fields Involved
DMC_CAL_
PADCTL0,
DMC_CAL_
PADCTL2
DMC_CTL.DDR3EN,
DMC_CTL.LPDDR
DMC_CTL.RDTOWR Make sure that the DMC_CTL.RDTOWR bit field is always set to 010
DMC_CFG
register
DMC_TR0,
DMC_TR1,
DMC_TR2
DDR3 DDR2
The DMC supports The DMC supports
ODT and drive impe- OCD calibration.
dance calibration. Configure the
DMC_CAL_
Configure the
DMC_CAL_ PADCTL0
and
PADCTL0 cordingly.
DMC_CAL_
registers
PADCTL2
accordingly. For de-
tails, refer PAD Cali-
bration for Driver Im-
pedance and On Die
Termination (ODT)
section.
Programming driver
impedance is required.
Programming ODT is
optional. To disable
ODT, set the
DMC_PHY_CTL1.
BYPODTEN bit.
Select DDR3 mode by Default is DDR2
setting the mode. Make sure that
DMC_CTL.DDR3EN
both the bits
bit. Make sure that the DMC_CTL.LPDDR
bit and
DMC_CTL.DDR3EN
DMC_CTL.LPDDR is
are cleared.
cleared.
(=2 in decimal).
Make sure that the DMC_CFG.IFWID and DMC_CFG.SDRWID bit
fields are always set to 0010 (=2 in decimal) as the DMC only supports
16-bit wide interface and SDRAM widths. Make sure that the bit field
DMC_CFG.EXTBANK is always set to 0000 as the DMC only sup-
ports one external bank. Select the DMC_CFG.SDRSIZE as per the
SDRAM size. Supported sizes are 64 Mb to 2 Gb for LPDDR, 256
Mb to 4 Gb for DDR2, and 512 Mb to 8 Gb for DDR3.
Configure the parameters t
RCD
t , t , t , t (DDR3/DDR2/LPDDR), and t
RRD WR XP CKE
(DDR3/DDR2) in terms of DCLK cycles.
DMC Programming Model
LPDDR
The DMC does not
support ODT and
drive impedance cali-
bration. No need to
register ac-
program the
DMC_CAL_
PADCTL0
DMC_CAL_
PADCTL2
Must make sure that
the
DMC_PHY_CTL1.
BYPODTEN bit is set
to bypass the process-
or ODT settings.
Select LPDDR mode
by setting the
DMC_CTL.LPDDR
bit. Make sure that the
bit
DMC_CTL.DDR3EN
is cleared.
, t , t , t , t , t
WTR RP RAS MRD REF
, t
FAW
and
registers.
, t ,
RFC
RTP
10–15