Adsp-Sc58X Cgu Trigger List; Cgu Definitions - Analog Devices ADSP-SC58 Series Hardware Reference Manual

Table 3-2: ADSP-SC58x CGU Interrupt List
Interrupt Name
ID
1 CGU0_EVT
2 CGU1_EVT

ADSP-SC58x CGU Trigger List

Table 3-3: ADSP-SC58x CGU Trigger List Masters
Trigger ID Name
1 CGU0_EVT
2 CGU1_EVT
Table 3-4: ADSP-SC58x CGU Trigger List Slaves
Trigger ID Name

CGU Definitions

DPM
The dynamic power management (DPM) works with the CGU to provide flexible power dissipation modes for the
processor.
PCU
The PLL control unit (PCU) in the CGU controls PLL operations. All the MMR registers of the CGU are imple-
mented in this unit.
PLL
The phase-locked loop (PLL) operates within the CGU.
RCU
The reset control unit (RCU) provides input to the CGU to manage clocks during processor reset.
CDU
The clock distribution unit distributes the clocks from the CGU to different clock domains
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Description
CGU0 Event
CGU1 Event
Description
CGU0 Event
CGU1 Event
Description
None
CGU Functional Description
Sensitivity DMA
Channel
Edge
Edge
Sensitivity
Edge
Edge
Sensitivity
3–3