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Status information about the PWM is available in the
interrupt status bits. In particular, the period boundary of each timer is available, as well as status bits. The PWM
uses the status bits to indicate whether the operation is in the first half or the second half of the timer. Additionally,
the TRIP status is also available. For more information on TRIP interrupts, see
Trip Control Unit
The PWM output signals can be shut-off in a number of different ways. The trip inputs (PWM_TRIP[n]) can be
mapped to provide either a temporary or permanent shutdown on any channel outputs (hi/lo/pair). This shutdown
mechanism is asynchronous so that the associated PWM output disable circuitry does not go through any clocked
logic. This functionality ensures correct PWM shutdown even in the event of a loss of the processor clock. In addi-
tion to the hardware shutdown features, the PWM system can be shut down in software with the
PWM_CTL.SWTRIP bit.
The external trip signal PWM_TRIP0, that comes from GPIO generates the TRIP0 input whereas the trigger slaves
PWM0_TRIP_TRIGn, PWM1_TRIP_TRIGn and PWM2_TRIP_TRIGn generate TRIP1 input.
During any external trip event (if not disabled), the PWM outputs are turned off. When a PWM output is turned
off, it means that the output level is held at a polarity opposite that given in the PWM_CHANCFG.POLAH through
PWM_CHANCFG.POLDH (channel high side polarity) bits. The PWM sync pulse continues to operate, when it is
already enabled. A PWMTRIP interrupt occurs if unmasked, to notify the software of this event. In dependent
mode of operation, both high and low-side outputs refer to the channel high side polarity bits.
Even if the clock to the PWM is damaged, an external trip event turns off the PWM outputs. In this case, the
PWMTRIP interrupt request may not occur.
The PWM trip unit processes hardware or software fault conditions and shuts down the PWM channel outputs
immediately on the occurrence of these conditions. The PWM can enable the shutdown mechanism separately for
each channel. The design also allows for a self-restart mechanism to be enabled on a channel. Self-restart reenables
the channel outputs following the fault condition (allowed only on hardware trips) when the PWMTMRy that the
channel is using reaches its period boundary.
These sources are active low inputs where a falling edge on either of these pins indicates a fault condition.
The trip unit can shut down an output of a particular channel in response to the fault event from the PWM_TRIP0
pin. To enable this functionality, program the PWM_TRIPCFG.EN0A bit corresponding to the channel.
Program the PWM_TRIPCFG.MODE0A bits to specify the restart mechanism for a channel that has been tripped.
1. If the PWM_TRIPCFG.MODE0A bit =0, once tripped, a trip condition is registered on this channel in the
PWM_STAT.FLTTRIPA bit and the outputs of that channel are immediately shut down. This condition is
called a fault trip condition. To resume channel output when a fault trip occurs, write a 1 to clear the
PWM_STAT.FLTTRIPA bit. A processor write cannot clear the bit when the trip condition is still active. The
raw trip status is available for both pins in the PWM_STAT.RAWTRIP0 register bits.
2. If the PWM_TRIPCFG.MODE0A bit =1, once tripped, a trip condition is registered on this channel in the
PWM_STAT.SRTRIPA bit and the outputs of that channel are immediately shut down. This condition is
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
PWM_STAT
register, which stores all status bits, including raw
Trip Control Unit
.
Event Control
19–33
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