Table of Contents
Advertisement
ADSP-SC58x CGU Register Descriptions
Time Stamp Control Register
The
register controls the operation of the CoreSight time stamp counter.
CGU_TSCTL
TSDIV (R/W)
Counter's Clock Divider
LOAD (R/W)
Load Counter
LOCK (R/W)
Lock
Figure 3-16: CGU_TSCTL Register Diagram
Table 3-22: CGU_TSCTL Register Fields
Bit No.
(Access)
31
LOCK
(R/W)
7:4
TSDIV
(R/W)
1
LOAD
(R/W)
0
EN
(R/W)
3–38
15
14
13
12
11
10
0
0
0
0
0
31
30
29
28
27
26
0
0
0
0
0
Bit Name
Lock.
Setting the CGU_TSCTL.LOCK bit locks this register.
Counter's Clock Divider.
The CGU_TSCTL.TSDIV bit field divides SYSCLK by 2
Load Counter.
Writing one to the CGU_TSCTL.LOAD bit causes CoreSight time stamp counter to
be loaded from the
Counter Enable.
The CGU_TSCTL.EN bit enables or disables the CoreSight time stamp counter.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
9
8
7
6
5
4
3
0
0
0
0
0
0
0
0
25
24
23
22
21
20
19
18
0
0
0
0
0
0
0
0
Description/Enumeration
0 Unlock
1 Lock
0-15 Divides SYSCLK by 2
CGU_TSVALUE0
0 Always read as "0"
0 Counter Disabled
1 Counter Enabled
2
1
0
0
0
0
EN (R/W)
Counter Enable
17
16
0
0
0
TSDIV
TSDIV
and
registers.
CGU_TSVALUE1
.
Advertisement
Table of Contents
