Analog Devices ADSP-SC58 Series Hardware Reference Manual page 420

DMC Event Control
The DMC can be brought out of self-refresh mode by clearing the DMC_CTL.SRREQ bit again. The controller
clears the DMC_STAT.SRACK bit after the self-refresh operation completes.
DMC Event Control
The DMC has no related interrupt or trigger event information.
DMC Programming Model
The dynamic memory controller contains five groups of memory-mapped registers. The DMC uses the MMR ac-
cess bus to connect to these registers.
• Control and status registers. These registers control the various operation modes of the dynamic memory con-
troller and provide status.
• Timing parameter registers. The value programmed in these registers depends on the speed grade of the
SDRAM device used.
• Mode register mirror registers. These shadow registers are copies of the mode registers residing in the SDRAM
device.
• PHY control and status registers. The DMC uses these registers to control the operation of the PHY.
• PAD control registers. The DMC uses these registers to control the various aspects of the I/O pads.
The DMC control registers contain sensitive timing parameters and settings for the DDR SDRAM. These registers
are programmed with values that are in the operating range of the DDR used.
Writing to reserved fields or writing any reserved values in register bits can cause the dynamic memory controller to
function erroneously.
Programming Considerations for DDR2, DDR3, and LPDDR Memory
The DDR2, DDR3, and LPDDR Programming table shows important programming considerations and differences
across DDR2, DDR3, and LPDDR memory technologies. The table serves as a quick reference when configuring
the DMC and PHY registers.
Table 10-9: DDR2, DDR3, and LPDDR Programming
PHY/Control- Description
ler
PHY Enabling DDR3/
DDR2/LPDDR
modes
10–14
Registers and Bit DDR3
Fields Involved
DMC_PHY_CTL4
Select DDR3 mode by
setting the
DMC_PHY_CTL4.
DDRMODE bit field to
00.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DDR2 LPDDR
Select DDR2 mode by Select LPDDR mode
setting by setting the
DMC_PHY_CTL4.
theDMC_PHY_CTL4
DDRMODE bit field to
.DDRMODE bit field
11.
to 01.