Table of Contents
Advertisement
Refresh Address Register
The
register stores the refresh address value. When this register is written, L2 initiates an atomic read-
L2CTL_RFA
write operation to the address value written into the register. This is a read/write register, but a new value in the
corresponding field has to be written only when there are no outstanding refresh request pending
(L2CTL_STAT.RFRS =0). If a write occurs while a request is pending, the L2CTL generates a bus error, and the
write does not take effect.
Figure 9-18: L2CTL_RFA Register Diagram
Table 9-19: L2CTL_RFA Register Fields
Bit No.
(Access)
31:16
ADDRHI
(R/NW)
15:0
ADDRLO
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15
14
13
0
0
0
ADDRLO (R/W)
Address Low
31
30
29
0
0
1
ADDRHI (R)
Address High
Bit Name
Address High.
The L2CTL_RFA.ADDRHI bits hold the high 16-bits of the L2 refresh address. Note
that the upper 14 bits are hard-coded to the upper bits of the L2 address map.
Address Low.
The L2CTL_RFA.ADDRLO bits hold the low 16-bits of the L2 refresh address. Note
that the lowest three bits are do-not-care.
12
11
10
9
8
7
6
5
0
0
0
0
0
0
0
0
28
27
26
25
24
23
22
21
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x L2CTL Register Descriptions
4
3
2
1
0
0
0
0
0
0
20
19
18
17
16
0
1
0
0
0
9–29
Advertisement
Table of Contents
