Analog Devices ADSP-SC58 Series Hardware Reference Manual page 724

Memory-Mapped Mode (SPI2 only)
Figure 16-14: Memory-Mapped Protocol
As shown in the figure, the COMMAND field (SPI_MMRDH.OPCODE) is transmitted upon assertion of the
SPI_SEL[n] signal. The SPI memory interprets this 8-bit value as a read command. Any 8-bit read opcode whose
timing is compliant with the processor SPI and features provided by memory-mapped hardware is allowed, the most
common being:
• Standard Read (0x03)
• Fast Read (0x0B)
• Fast Read Dual Output (0x3B)
• Fast Read Dual I/O (0x6B)
• Fast Read Quad Output (0xBB)
• Fast Read Quad I/O (0xEB)
• Word Read Quad I/O (0xE7)
• Octal Word Read Quad I/O (0xE3)
NOTE: The SPI hardware does not validate the content of the SPI_MMRDH.OPCODE field prior to transmitting.
DMYSIZE (Number of Dummy Bytes)
When operating at a high clock frequency in multi-IO modes, most flash devices require some dummy clocks after
the address bits. These dummy clock cycles allow the internal circuits of the device extra time for setting up the
initial address. These bits specify the number of bytes separating address transmission and read data return.
The number of dummy cycles required varies per manufacturer, the read command used, and the SPI access time.
The SPI hardware allows dummy cycles to be programmed in bytes in the SPI_MMRDH.DMYSIZE field, the value
16–18
SPI CONTROLLER
MEMORY-MAPPED
CS GAP
MODE SETTINGS
LAG LEAD STOP COMMAND ADDRESS
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
RECEIVED DATA
(CACHE LINE)
DUMMY W0 W1 W2 W3
W0 W1 W2 W3
W0 W1 W2 W3
APPLICATION
ADDRESS
W0 W1 W2 W3
W4 W5 W6 W7
INTERNAL
FLASH
MEMORY
W4 W5 W6 W7
W4 W5 W6 W7
W4 W5 W6 W7