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UART Architectural Concepts
• The transmit and receive request outputs can function as DMA requests and connect to the DMA controller.
Therefore, if the DMA is not enabled, the DMA controller simply forwards the request to the system event
controller (SEC).
• The status interrupt output connects directly to the SEC. On many processors, the alternative capture input
(TIMER_ACI[n]) of one of the GP timers also senses the UART_RX pin. When configured in capture mode,
the processor can then use the GP timer to detect the bit rate of the received signal.
External Interface
Each UART features a UART_RX (receive) pin and a UART_TX (transmit) pin available through the general-pur-
pose ports. These two pins usually connect to an external transceiver device that meets the electrical requirements of
full-duplex or half-duplex standards. For example, EIA-232, EIA-422, 4-wire EIA-485 for full-duplex or 2-wire
EIA-485, LIN for half-duplex. Additionally, the UART features a pair of clear-to-send, input pins (UART_CTS),
and request-to-send, output pins (UART_RTS) for hardware flow control. UART signals are multiplexed with other
functions at the pin level.
Hardware Flow Control
To prevent the UART transmitter from sending data while the receiving counterpart is not ready, the UART features
a UART_RTS/UART_CTS hardware flow control mechanism. The UART_RTS signal is an output that connects to
the UART_CTS input of the communication partner. If data transfer is bidirectional, the figure shows the UART
Hardware Flow Control handshake.
Figure 17-2: UART Hardware Flow Control
In both DMA and core mode, the receiver can deassert the UART_RTS signal to indicate that its receive buffer is
almost full. Continued data transfers can cause an overrun error. The transmitter pauses when the UART_CTS in-
put is in a deasserted state. In this state, the transmitter completes transmission of the data currently held in the
transmit shift register (UART_TSR) but it does not continue with the data in the transmit hold register
(UART_THR). If the UART_CTS pin is asserted again, the transmitter resumes and loads the content of
register into the
UART_THR
Bit Rate Generation
The peripheral clock (SCLK0_0) and the 16-bit divisor in the
The UART uses the UART_CTL.EN bit to enable the clock. By default, every serial bit is oversampled 16 times.
17–6
PROCESSOR
UARTx
UARTxTX
UARTxRX
UARTxRTS
UARTxCTS
register.
UART_TSR
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
OTHER UART
DEVICE
TX
RX
RTS
CTS
register characterize the sample clock.
UART_CLK
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