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Channel Timing Control Unit
The channel timing control unit is the core of the PWM. There are four separate channels, each channel controlling
a pair of output signals – the high-side output and the low-side output.
Channel Control
The
PWM_CHANCFG
register controls the static configuration of all the channels and is initialized once before the
beginning of a PWM operation.
NOTE:
The
PWM_CHANCFG
PWM is enabled.
Each channel works with a reference timer base. The time base can be either the main timer PWMTMR0 or the
appropriate PWMTMRx. Configure the time base with the PWM_CHANCFG.REFTMRA bit field as follows.
• Channel A works with PWMTMR0 or PWMTMR1
• Channel B works with PWMTMR0 or PWMTMR2
• Channel C works with PWMTMR0 or PWMTMR3
• Channel D works with PWMTMR0 or PWMTMR4
The double-buffered channel control registers
namic pulse behavior of the channel outputs. These registers have bits that enable or disable outputs and select the
pulse position of outputs (explained in the following section).
Pulse Positioning and Duty Cycle Registers
The PWM uses the PULSEMODEHI and PULSEMODELO bit fields of the PWM_[n]CTL registers to define the
region within the timer period where the output pulses are positioned.
• When the PWM_CHANCFG.MODELSC bit is 0, the PWM uses the PULSEMODEHI field to specify the pulse
positioning for both the high-side and low-side outputs of the channel.
• When the bit is 1, the PWM uses PWM_ACTL.PULSEMODELO to define the pulse positioning for the low-
side output of the channel. It uses the PWM_ACTL.PULSEMODEHI to define the pulse positioning for the
high-side output of the channel.
Each channel output has two duty-cycle registers:
PWM_AL0
and
PWM_AL1
the PWM_CHANCFG.MODELSC bit is 0, the high-side duty-cycle registers are used to determine the width of the
output pulse for the low side. The duty cycle range that can be programmed into these registers is between –
PWM_TM[n]/2 and +PWM_TM[n]/2 , when ignoring dead time.
When including dead time for channel A, for PULSEMODEs 00 and 01, the programmed duty cycle is modified.
The range is limited between the values [–PWM_TM[n]/2 + PWM_CHA_DT] and [+PWM_TM[n]/2 +
PWM_CHA_DT] considering the high-side output. For PULSEMODEs 10 and 11, the high-side duty cycle registers
range is limited between values [PWM_TM[n]/2 + PWM_CHA_DT] and [–PWM_TM[n]/2 – PWM_CHA_DT].
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register is not double buffered. Do not change the contents of the register once the
(PWM_ACTL
PWM_AH0
for the low-side output. These registers determine the width of the output pulses. When
through PWM_DCTL) contain bits that control the dy-
and
for the high-side output, and
PWM_AH1
Architectural Concepts
19–13
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