Analog Devices ADSP-SC58 Series Hardware Reference Manual page 823

ADSP-SC58x UART Register Descriptions
Interrupt Mask Clear Register
The indicates interrupt mask status (unmasked if set, masked if cleared) of UART status interrupts.
UART_IMSK
This register is not a data register. Instead it is controlled by the
ter pair. Writing ones to
disables (masks) them. Reads from either register return the enabled bits. For more informa-
UART_IMSK_CLR
tion, see the UART_IMSK
ETXS (R/W1C)
Enable TX to Status Interrupt Mask
Clear
ERXS (R/W1C)
Enable RX to Status Interrupt Mask
Clear
EAWI (R/W1C)
Enable Address Word Interrupt Mask
Clear
ERFCI (R/W1C)
Enable Receive FIFO Count Interrupt
Mask Clear
ETFI (R/W1C)
Enable Transmission Finished Interrupt
Mask Clear
Figure 17-14: UART_IMSK_CLR Register Diagram
Table 17-13: UART_IMSK_CLR Register Fields
Bit No.
(Access)
9 ETXS
(R/W1C)
8 ERXS
(R/W1C)
7 EAWI
(R/W1C)
17–36
UART_IMSK_SET enables (unmasks) interrupt requests, and writing ones to
register description.
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
31 30 29 28 27 26 25 24
0 0 0 0 0 0 0 0
Bit Name
Enable TX to Status Interrupt Mask Clear.
Enable RX to Status Interrupt Mask Clear.
Enable Address Word Interrupt Mask Clear.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
UART_IMSK_SET
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
23 22 21 20 19 18 17 16
0 0 0 0 0 0 0 0
Description/Enumeration
0 No action
1 Mask interrupt
0 No action
1 Mask interrupt
0 No action
1 Mask interrupt
and UART_IMSK_CLR
ERBFI (R/W1C)
Enable Receive Buffer Full Interrupt
Mask Clear
ETBEI (R/W1C)
Enable Transmit Buffer Empty Interrupt
Mask Clear
ELSI (R/W1C)
Enable Line Status Interrupt Mask Clear
EDSSI (R/W1C)
Enable Modem Status Interrupt Mask
Clear
EDTPTI (R/W1C)
Enable DMA TX Peripheral Triggered
Interrupt Mask Clear
regis-