Analog Devices ADSP-SC58 Series Hardware Reference Manual page 257

SEC Functional Description
Table 7-3: ADSP-SC58x Combined SEC and GIC Interrupt List (Continued)
Module Event/Interrupt
PCIE PCIe Status
PCIE PCIe DMA Completion
TRU TRU0 Interrupt 0, core ID = 0
TRU TRU0 Interrupt 1, core ID = 0
TRU TRU0 Interrupt 2, core ID = 0
TRU TRU0 Interrupt 3, core ID = 0
CTI CTI Event0, core ID = 0
PMU Performance Monitoring Interrupt, core ID = 0
SEC Definitions
The event controller uses the following definitions.
System Events
System source indications including interrupts and faults.
System Source
Point of origin of system event.
SID (Identification, unique)
Source numeric identifier for each system source connected to the SEC.
SSI
SEC source interface, system event source control, and status subblock of the SEC.
SCI
SEC core interface, core interface subblock of the SEC
SPR
SEC prioritizer determines the highest priority pending interrupt and the highest priority active interrupt. The SPR
provides these interrupts in the appropriate registers of the SCI for the priority and nesting model of the SCI.
7–12
SEC ID GIC ID
244 276
245 277
246 − 247 278 − 279
Reserved Reserved
Reserved 280
Reserved 281
Reserved 282
Reserved 283
Reserved 284
Reserved 285
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SEC/GIC Interrupt Name
PCIE0_STAT
PCIE0_DMA
TRU_INT0
TRU_INT1
TRU_INT2
TRU_INT3
ECT_C0_EVT
C0_PMUIRQ