Analog Devices ADSP-SC58 Series Hardware Reference Manual page 717

For example, assume that the SPI of the processor is the master. The SPI_SLVSEL.SSEL1 –
SPI_SLVSEL.SSEL7 bits on the processor can be connected to the slave select pin of each slave device. In this
configuration, the slave select bits can be used in three ways. In cases 1 and 2, the processor is the master and the
seven microcontrollers or peripherals with SPI interfaces are slaves. The processor can do one of the following:
1. Transmit to all seven SPI devices at the same time in a broadcast mode. Here, all slave select bits are set.
2. Receive and transmit from one SPI device by enabling only one slave SPI device at a time.
3. If all the slaves are also processors, then the requester can receive data from only one processor at a time. (The
functionality is enabled by clearing the SPI_CTL.EMISO bit in the six other slave processors.) The requestor
can transmit broadcast data to all seven at the same time. This MISO enabling feature is available in some
other microcontrollers. Therefore, it is possible to use the MISO enabling feature with any other SPI device
that includes this functionality.
SLAVE DEVICE
SPI_MISO SPI_CLK SPI_MOSI
Figure 16-7: Single-Master, Multiple-Slave Configuration
Beginning and Ending a Non-DMA SPI Transfer
The start and finish of a non-DMA SPI transfer depend on the following settings.
1. Whether the device is configured as a master or a slave.
2. The state of the SPI_CTL.ASSEL bit, which selects between hardware and software control over
SPI_SLVSEL.
When SPI_CTL.CPHA=0, the enabled slave select outputs are driven active. However, the SPI_CLK signal re-
mains inactive for the first half of the first cycle of SPI_CLK. For a slave with SPI_CTL.CPHA=0, the transfer
starts as soon as the SPI_SS input goes low.
When SPI_CTL.CPHA=1, a transfer starts with the first active edge of SPI_CLK for both slave and master devi-
ces. For a master device, a transfer is complete after it sends the last data and simultaneously receives the last data bit.
A transfer for a slave device ends after the last sampling edge of SPI_CLK. If SPI_CTL.ASSEL=0, the hardware
maintains responsibility for toggling SPI_SS between frames. If SPI_CTL.ASSEL=1, software controls the
SPI_SS line and can keep it active between frames.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SLAVE DEVICE
SPI_MISO SPI_CLK SPI_MOSI
SPI_SS
SLAVE DEVICE
SPI_MISO SPI_CLK SPI_MOSI
SPI_SS
SPI_CLK SPI_MOSI
SPI_MISO
SPI_SEL1
MASTER
SPI_SEL2
DEVICE
SPI Functional Description
SPI_SS
VDD
SPI_SS
SPI_SEL3
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