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Shared Peripheral Interrupt Priority Register
The
GICDST_SPI_PRIO[n]
This field stores the priority of the corresponding interrupt.
Figure 7-58: GICDST_SPI_PRIO[n] Register Diagram
Table 7-61: GICDST_SPI_PRIO[n] Register Fields
Bit No.
(Access)
0
VALUE
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
registers provide an 8-bit priority field for each interrupt supported by the GIC.
VALUE (R/W)
Priority
Bit Name
Priority.
The GICDST_SPI_PRIO[n].VALUE bit field stores the priority of the corre-
sponding interrupt (byte offset 3 to Byte offset 0).
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x GICDST Register Descriptions
7–91
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