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Timing 2 Register
The
register selects timing parameters for DMC operation to corresponding with parameters of the
DMC_TR2
SDRAM device that is used in the system. The timing registers must be programmed to match the device for correct
operation of the SDRAM and before initializing the SDRAM.
Note that all values for bit fields in
TWR (R/W)
Timing Write Recovery
TRTP (R/W)
Timing Read-to-Precharge
TCKE (R/W)
Timing Clock Enable
Figure 10-27: DMC_TR2 Register Diagram
Table 10-36: DMC_TR2 Register Fields
Bit No.
(Access)
23:20
TCKE
(R/W)
19:16
TXP
(R/W)
15:12
TWR
(R/W)
11:8
TRTP
(R/W)
4:0
TFAW
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
are in increments of clock cycle time (t
DMC_TR2
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit Name
Timing Clock Enable.
The DMC_TR2.TCKE field selects the CKE minimum pulsewidth (t
Timing Exit Power Down.
The DMC_TR2.TXP field selects the exit power down to next valid command time
(t
).
XP
Timing Write Recovery.
The DMC_TR2.TWR field selects the write recovery time (t
eter applies to LPDDR only.
Timing Read-to-Precharge.
The DMC_TR2.TRTP bit field selects the internal read to precharge time (t
DDR2/DDR3 modes. If the resulting value in DDR2/DDR3 mode is less than 2,
program the bit field to 2. This value (2) is the minimum t
mode.
For LPDDR mode program this bit field to zero.
Timing Four-Activated-Window.
The DMC_TR2.TFAW field selects the four-banks-activated window time (t
more than four SDRAM banks should be activated within this window.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Description/Enumeration
ADSP-SC58x DMC Register Descriptions
).
CK
TFAW (R/W)
Timing Four-Activated-Window
TXP (R/W)
Timing Exit Power Down
). Note that this param-
WR
time for DDR2/DDR3
RTP
).
CKE
) for
RTP
). No
FAW
10–67
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