Analog Devices ADSP-SC58 Series Hardware Reference Manual page 277

Sharc+ processor
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ADSP-SC58x SEC Register Descriptions
Core Pending Register n
The SCI pending interrupt register (SEC_CPND[n]) contains the source ID and priority of the highest priority
pending interrupt detected by the SEC prioritizer.
PRIO (R)
Highest Pending IRQ Priority
Figure 7-11: SEC_CPND[n] Register Diagram
Table 7-10: SEC_CPND[n] Register Fields
Bit No.
(Access)
15:8
PRIO
(R/NW)
7:0
SID
(R/NW)
7–32
15
14
13
12
11
10
9
8
0
0
0
0
0
0
0
0
31
30
29
28
27
26
25
24
0
0
0
0
0
0
0
0
Bit Name
Highest Pending IRQ Priority.
The SEC_CPND[n].PRIO indicates the priority value of the highest priority pend-
ing interrupt for core n.
Highest Pending IRQ Source ID.
The SEC_CPND[n].SID identifies the source ID value of the highest priority pend-
ing interrupt for core n.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
23
22
21
20
19
18
17
16
0
0
0
0
0
0
0
0
Description/Enumeration
SID (R)
Highest Pending IRQ Source ID

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