Changing The Oclk Frequency; Aligning All Clocks - Analog Devices ADSP-SC58 Series Hardware Reference Manual

Writing to the CGU_DIV
the write is visible only after the transition to full-on (PLL not bypassed) mode.
Accessing the DDR memory while changing the SYSCLK frequency is not supported and can have unpredictable
results.

Changing the OCLK Frequency

To change the OCLK clock frequency, write a new CGU_DIV.OSEL bit value. Any time the OCLK clock frequen-
cy is changed, the OCLK, CCLKn, SYSCLK, and SCLKn clocks exit the frequency change sequence aligned.
1. Read the CGU_STAT
2. Write the desired CGU_DIV.OSEL value with the CGU_DIV.UPDT bit =1.
ADDITIONAL INFORMATION: This write updates the
and aligns all clocks except OCLK.
The CGU_STAT register exits this sequence with the CGU_STAT.CLKSALGN bit =0. Poll the
CGU_STAT.CLKSALGN bit to discover when the clocks are aligned. Any write attempt to change the
CGU_DIV.DSEL field while the CGU_STAT.CLKSALGN bit =1 (clock alignment in progress) triggers an MMR
access bus error and the
Writing to the CGU_DIV.OSEL bit field is allowed while the processor is in active (PLL bypassed) mode. But, the
effect of the write is visible only after the transition to full-on (PLL not bypassed) mode.

Aligning All Clocks

To align the clocks, write 1 to the CGU_DIV.ALGN bit. The frequency can be changed, if necessary. The clocks
aligned include:
• CCLKn
• SYSCLK
• SCLKn
• DCLK
• OCLK
1. Read the CGU_STAT
2. Write 1 to the CGU_DIV.ALGN bit. All other fields can change.
ADDITIONAL INFORMATION: This write does not alter the
lect fields is modified. When the clocks are aligned, a CGU event occurs.
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
register is allowed while the processor is in active (PLL bypassed) mode. But, the effect of
register to verify that the CGU_STAT.CLKSALGN bit =0 (clocks aligned).
CGU_DIV register is not modified. When the clocks are aligned, a CGU event occurs.
register to verify that CGU_STAT.CLKSALGN bit =0 (clocks aligned).
register, changes the OCLK frequency,
CGU_DIV
CGU_DIV register unless one of the clock-se-
Configuring CGU Modes
3–11