Analog Devices ADSP-SC58 Series Hardware Reference Manual page 151

Table 2-5: L2CC Configuration Signals (Continued)
Configuration
Cache controller cache ID
Address filtering Enable out of reset
Address filtering End Address out of reset
Address filtering Start Address out of reset
Endian mode for accessing configuration registers out of reset
Base address for accessing configuration registers
Size of ways
L2CC Power Down Modes
Table 2-6: L2CC Power Down Modes
Mode
Run mode
Dynamic Clock Gating
Standby mode
Dormant mode
Shutdown mode
L2CC Configuration
Table 2-7: L2CC Configuration
Feature
Cache way size
Associativity
Default RAM latencies
DATA RAM banking
Slave port 1 present
Master port 1 present
Parity logic
Lock down by master
Lock down by line
Address filtering
Speculative reading
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
L2CC TRM Signal Name
CACHEID[5:0]
CFGADDRFILTEN
CFGADDRFILTEND[11:0]
CFGADDRFILTSTART[11:0]
CFGBIGEND
REGFILEBASE[19:0]
WAYSIZE[2:0]
Comment
Supported
Supported
Not Supported
Not Supported
Not Supported
Comment
32 KB
8 Ways
2 cycles
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled
Functional Description
Comment
0
Enabled
0xFFF
0x201
Little-endian
0x10000
32 KB
2–9