Analog Devices ADSP-SC58 Series Hardware Reference Manual page 422

DMC Programming Model
Table 10-9: DDR2, DDR3, and LPDDR Programming (Continued)
PHY/Control- Description
ler
Controller Configuring burst
length
Controller Configuring CAS la-
tency
Controller Configuring the
DMC_MR.DLLRST
bit (DDR2/LPDDR)
or
DMC_MR0(DDR3)
Write recovery timing DMC_MR.WRRECOV
Controller
Controller Configuring
DMC_MR1(DDR3)
or
DMC_EMR1
(DDR2) register
Controller Configuring
DMC_MR2(DDR3)
or
DMC_EMR2
(DDR2) or
DMC_EMR
(LPDDR) register
10–16
Registers and Bit DDR3
Fields Involved
DMC_MR.BLEN (for The DMC only sup-
DDR2 and LPDDR), ports burst length of
DMC_MR0.BLEN 8. Configure the
for DDR3 DMC_MR0.BLEN
field to 00 only.
DMC_MR.CL (for The DMC supports
DDR2 and LPDDR), CAS latencies of 5
DMC_MR0.CL0, to14. Refer to the
and DMC_MR0.CL DMC_MR.CL register
(for DDR3) description for more
details.
DMC_MR.DLLRST/ Set this bit while per-
forming the initializa-
DMC_MR0.DLLRS
tion
T
The DMC supports
and
WR values of 5 to 16.
DMC_MR0.WRRE-
Refer to the
COV
DMC_MR0 register
description for more
details.
DMC_MR1(DDR3) The DMC can use this register to configure
or DMC_EMR1 memory drive impedance, ODT, and additive
latency parameters. Refer to the corresponding
(DDR2)
register descriptions for more details.
DMC_MR2(DDR3) Configure the write
or latency field (CWL)
to the required value.
DMC_EMR2(DDR2)
or DMC_EMR The DMC can also
(LPDDR) use this register to en-
able Auto Self-Refresh
(ASR) and to select
Self-Refresh Tempera-
ture (SRT) functional-
ities in the memory
device. For more de-
tails on these func-
tionalities, refer to the
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
DDR2 LPDDR
The DMC supports The DMC supports
both burst length of 4 both burst length of 4
and 8. Configure and 8. Configure
DMC_MR.BLEN field DMC_MR.BLEN field
to 10 for burst length to 10 for burst length
of 4 and to 11 for of 4 and to 11 for
burst length of 8 burst length of 8
words. words.
The DMC supports The DMC supports
CAS latencies of 3 to CAS latency of 3. Re-
6. Refer to the fer to the
DMC_MR register de- register description for
scription for more de- more details.
tails.
Setting of this bit is Reserved
optional for DDR2.
The DMC supports Reserved
WR values of 2 to 8.
Refer to the
DMC_MR
register description for
more details.
This register is not
used for LPDDR pro-
gramming.
The DMC can use The DMC can use
this register to config- this register to config-
ure the Partial Array ure the Partial Array
Self-Refresh (PASR) Self-Refresh (PASR),
and High Tempera- Temperature compen-
ture Self-Refresh Rate sated self-refresh
Enable (SRF) func- (TCSR), and drive
tionalities of DDR2 strength (DS) func-
memory device. For tionalities of the mem-
more details on these ory device. For more
functionalities, refer to details on these func-
the DDR2 memory tionalities, refer to the
device data sheet. LPDDR memory de-
vice data sheet.
DMC_MR