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SPI Programming Concepts
Table 16-16: SPI Error Interrupts (Continued)
Bit
SPI_STAT.ROR
SPI_STAT.TC
SPI Programming Concepts
The following sections provide general programming guidelines and procedures.
Programming Guidelines
It is acceptable to program
However, program the initiating mode register and its counter-register, if enabled, after the non-initiating mode reg-
ister. For example, if transmit is the initiating mode and receive is the non-initiating mode, then program the
SPI_RXCTL
and
SPI_RWC
and receive in initiating mode, enable the
SPI_TXCTL
registers.
These programming guidelines prevent SPI from starting a transfer when SPI registers are not fully programmed.
Other ways of programming are also allowed as long as the initiating conditions prevent the start of communication
until after programming of SPI registers is complete.
Take precautions to avoid data corruption when changing the SPI module configuration. Do not change the config-
uration during a data transfer. Additionally, change the clock polarity only when no slaves are selected. However, an
exception to this rule exists. When an SPI communication link consists of a single master and slave,
SPI_CTL.ASSEL = 0. The slave select input of the slave is permanently tied low. In this case, the slave is always
selected. Avoid data corruption by enabling the slave only after both the master and slave devices are configured.
The module supports 8, 16-bit and 32-bit word sizes. To ensure correct operation, configure both the master and
slave with the same word size.
Master Operation in Non-DMA Modes
This section describes the operation of the SPI as a master in non-DMA mode.
16–30
Description
Reception error. Signaled when an overflow condition occurs on the receive channel. This event occurs when
a new data word is received, but the
receive initiating mode since
Transmit collision error. Signaled when loading data to the transmit shift register happens near the first trans-
mitting edge of SPI_CLK. In slave mode of operation, the SPI controller is unaware of when the next trans-
fer starts. Loading of data to the transmit shift register can happen just after the transmitting edge. This event
results in the setup time not being met for the first bit transmitted. The transmitted data is corrupt. In
SPI_CTL.CPHA 1 mode, the first SPI_CLK edge is taken as the first transmitting edge. If
SPI_CTL.CPHA =0, then the last SPI_CLK edge of the last transmission (SPI_CTL.SELST =1) or slave
select deassertion (SPI_CTL.SELST =0) is taken as the first transmitting edge. This error is signaled only in
the slave mode of operation. In master mode of operation, loading of data happens before the first transmit-
ting edge of SPI_CLK.
SPI_RXCTL
and
SPI_TXCTL
registers before the
SPI_CTL
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
SPI_RFIFO
is full. This error condition does not occur in master
Not Full is one of the conditions for transfer initiation.
SPI_RFIFO
registers after programming the
SPI_TXCTL
and
SPI_TWC
register after programming both the
SPI_CTL
registers. If enabling both transmit
SPI_RXCTL
register.
and
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