Analog Devices ADSP-SC58 Series Hardware Reference Manual page 435

Table 10-13: DMC_CTL Register Fields (Continued)
Bit No.
(Access)
8 ADDRMODE
(R/W)
7 RESET
(R/W)
6 PREC
(R/W)
5 DPDREQ
(R/W)
4 PDREQ
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Bit Name
Addressing (Page/Bank) Mode.
The DMC_CTL.ADDRMODE bit selects whether the DMC uses page or bank inter-
leaving for addressing. When using page interleaving, the bank address bits follow the
most significant column address bits. When using bank interleaving, the bank address
bits follow the most significant row address bits.
Reset SDRAM.
The DMC_CTL.RESET bit starts the reset sequence. Note that this bit always reads as
0.
Precharge.
The DMC_CTL.PREC bit enables precharge, which closes DRAM rows immediately
after access. When disabled, all accesses result in the respective DRAM rows remaining
open, until the DMC needs to close them.
Deep Power-Down Request.
The DMC_CTL.DPDREQ bit enables deep power-down mode if low power DMC op-
eration is enabled (DMC_CTL.LPDDR =1). When the processor does not require the
data stored in SDRAM (assume reset state of SDRAM), the DMC may put the
SDRAM in deep power-down mode. When the DMC is in deep power-down mode,
any data accesses cause the DMC to generate a bus error. The DRAM remains in deep
power-down mode as along as this bit is 1.
Power Down Request.
The DMC_CTL.PDREQ bit enables power-down mode. When the DMC is in power-
down mode, any data accesses cause the DMC to generate a bus error. The DRAM
remains in power-down mode as along as this bit is 1.
ADSP-SC58x DMC Register Descriptions
Description/Enumeration
0 Bank Interleaving
1 Page Interleaving
0 No effect
1 Starts reset sequence
0 No Effect
1 Enable Precharge
0 Disable Deep Power-Down
1 Enable Deep Power-Down
0 Disable Power-Down
1 Enable Power-Down
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