Table of Contents
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Data Address Alignment .................................................................................................................. 38–10
Descriptor Set Address Alignment ................................................................................................... 38–10
DMA Channel Peripheral DMA Bus................................................................................................... 38–11
Peripheral Control Commands ........................................................................................................ 38–11
Peripheral-Control Command Restrictions ...................................................................................... 38–13
Memory DMA and Triggering ............................................................................................................ 38–14
Medium Band Width DMA Channel MMR Access Bus ..................................................................... 38–16
DMA Channel Operation Flow........................................................................................................... 38–17
Startup Flow .................................................................................................................................... 38–17
Refresh Flow .................................................................................................................................... 38–18
Work Unit Transition Flow .............................................................................................................. 38–19
Transfer Termination and Shutdown Flow ....................................................................................... 38–22
DMA Channel Errors.......................................................................................................................... 38–23
Status and Debug Errors .................................................................................................................. 38–23
DMA Configuration Register Errors ................................................................................................ 38–24
Illegal Register Write During Run.................................................................................................... 38–25
Address Alignment Error.................................................................................................................. 38–25
Memory Access Error ....................................................................................................................... 38–25
Trigger Overrun Error ..................................................................................................................... 38–25
Bandwidth-Monitor Error................................................................................................................ 38–25
Control Interface Error .................................................................................................................... 38–25
DMA Operating Modes............................................................................................................................. 38–25
Register-Based Flow Modes ................................................................................................................... 38–26
Stop Mode........................................................................................................................................... 38–26
Autobuffer Mode................................................................................................................................. 38–26
Descriptor-Based Flow Modes ............................................................................................................... 38–26
Descriptor-Array Mode ....................................................................................................................... 38–27
Descriptor-List Mode .......................................................................................................................... 38–28
Descriptor-On-Demand Modes........................................................................................................... 38–29
Data Transfer Modes .............................................................................................................................. 38–29
Two-Dimensional DMA...................................................................................................................... 38–30
DMA Channel Event Control.................................................................................................................... 38–31
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
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Table of Contents
