Analog Devices ADSP-SC58 Series Hardware Reference Manual page 933

Timer Units
Figure 19-5: Impact of New DELAY Value on Timer Count for Equal Timer Periods
Case 2: PWM_TM0 = N x PWM_TMy
In this case, within a single period of PWMTMR0 a program can fit multiple periods (N) of PWMTMRy. Addi-
tionally, the channel delay register is triggered only once every N periods of PWMTMRy.
The operation is as follows: Every Nth period of PWMTMRy, PWMTMRy expects a synchronization pulse from
the PWM_DLY[n] register. When this register counts out that period and the trigger has not yet arrived,
PWMTMRy waits at the end of the period for the trigger. PWMTMRy starts counting down once the trigger ar-
rives. If the trigger comes earlier, PWMTMRy restarts immediately without waiting to complete the period count.
In the intervening periods, PWMTMRy operates independently. As the period ends, PWMTMRy reloads and starts
the next period without intervention from the channel delay register.
The Impact of DELAY Value Change for the Multiple Timer Periods shows an example with N = 2. PWMTMRy
syncs up with PWMTMR0 every second period, and is free running across every odd period boundary.
Figure 19-6: Impact of DELAY Value Change for Multiple Timer Periods
19–12
PWMTMR0
PWM_BH
More than one period
CASE A: Increasing DELAY
DELAY1
PWM_DLYA
PWMTMR1
PWM_AH
PWMTMR0
PWM _BH
DELAY1
Case A: Increasing Delay
PWM_DLYA
PWMTMR1 Period starts unhindered
PWM _AH
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
Less than one period
CASE B: Decreasing DELAY
DELAY2 DELAY1
TMR1 forced to
restart period
TMR1
waits
DELAY2 Case B: Decreasing Delay DELAY1
Period starts unhindered
Re- synced at every Nth period Re- synced at every Nth period